3.3V to 1.8V and 0.9V step-down DC-DC converter
3.3V to 1.8V and 0.9V step-down DC-DC converter
- TSMC
- 28nm
3.3V to 1.8V and 0.9V step-down DC-DC converter
3.3V to 1.8V and 0.9V step-down DC-DC converter
<4Gbps Low Power D2D Interface in TSMC 16nm & 28nm
A
Low Power D2D Interface in TSMC 16nm FFC/FFC+
A 600MBps Low Power Die-to-Die Interface in TSMC 16nm FFC/FFC+.
4.3GHz SSCG PLL on TSMC 7nm
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices.
5A DCDC, 0.60...1.43V switching regulator using COT switch mode, Vin=4.25...15V
5A DCDC, 0.60...1.43V switching regulator using COT switch mode, Vin=4.25...15V
10/100/1000 base T ethernet Phy
IP
IP
IP
Clock latched comparator for 2V supply and PMOS type input designed in 0.18um 6M TSMC technology.
IP
Analog comparator for 3.6V supply and PMOS type input designed in 0.18um 6M TSMC technology
IP
The sCODa95-H1-LR_08 is a feature-rich audio CODEC which provides the insurance of the best sound quality after integration into …
TSMC N3P 1.2V IO Platform supporting cells
TSMC N3P 1.2V IO Platform supporting cells
TSMC N3P 1.8V IO Platform supporting cells
TSMC N3P 1.8V IO Platform supporting cells
Sofics specialty I/Os offer configurable GPIOs with multi-voltage support, over-voltage tolerance (OVT), and high-speed or ultra-low-power modes.
12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
The A12B400M is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block.
12-bit, 200 MSPS Pipeline ADC - TSMC 28nm
The A12B200M is a low-power, analog to digital converter (ADC) intellectually property (IP) design block.
UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
PCIe 7.0 PHY in TSMC (N5, N3P)
The multi-channel PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across back…