Foundation Library IP cores provide the fundamental building blocks required for ASIC and SoC implementation, enabling efficient digital design, physical synthesis, timing closure, and manufacturing across advanced semiconductor process nodes.
This category includes both Standard Cell Libraries and I/O Pad Libraries, covering logic cells, sequential elements, low-power cells, level shifters, ESD-protected I/O interfaces, and process-specific implementation libraries optimized for leading foundries.
This catalog enables semiconductor engineers to evaluate and compare Foundation Library IP solutions from multiple vendors based on process node support, PPA (Power, Performance, Area) characteristics, library characterization quality, voltage domains, reliability requirements, and integration with modern EDA design flows.
Whether targeting AI accelerators, automotive SoCs, networking devices, wireless chipsets, or high-performance computing applications, engineers can identify the Foundation Library IP best suited to their technology, performance, and manufacturing requirements.
9 track standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLPeF Sesame 9T a unique architecture based on 9-track cells, optimized for High Density and Low Dynam…
SSTL with bi-directional I/O’s, Vref, and ODT for DDR2 memory (1.8 V)
The DDR2 / DDR3 library includes the combo driver / receiver cells and a full complement of power and support cells for both sing…
6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi…
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi…
6 track Ultra High Density standard cell library at TSMC 130 nm
TSMC 130 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi…
6 track Ultra High Density standard cell library at TSMC 130 nm
Foundry Sponsored, TSMC 130 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latc…
6 track High Density standard cell library at TSMC 180 nm
Foundry Sponsored, TSMC 180 eLL, SESAME HD DV provides the best trade-off between area and power achieved from an cell design ena…
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufactur…
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufactur…
DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.
DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm
The DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM devi…
Specialed 20V Analog I/O in TSMC 55nm
A TSMC 55nm LP Specialized 20V Analog I/O in Standard Low Voltage CMOS This silicon-proven TSMC 55nm LP 20V ESD cell is a high-vo…
Differential IO Buffer on TSMC CLN7FF
The Differential IO Buffer macros provide a low noise, high performance differential output clock that is compatible with HCSL (H…
Differential IO Buffer on TSMC CLN16FFC
The Differential IO Buffer macros provide a low noise, high performance differential output clock that is compatible with HCSL (H…
Differential IO Buffer on TSMC CLN12FFC
The Differential IO Buffer macros provide a low noise, high performance differential output clock that is compatible with HCSL (H…
CML Differential IO Buffer on TSMC CLN6FF
The CML to HCSL Differential IO Buffer macros provide a low noise, high performance differential output clock that is compatible …
ECO Library IPs at TSMC 55ULPEF Process
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ECO Library IPs at TSMC 55ULP Process
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ECO Library IPs at TSMC 40ULPEF Process
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ECO Library IPs at TSMC 40ULP Process
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