Foundation Library IP cores provide the fundamental building blocks required for ASIC and SoC implementation, enabling efficient digital design, physical synthesis, timing closure, and manufacturing across advanced semiconductor process nodes.
This category includes both Standard Cell Libraries and I/O Pad Libraries, covering logic cells, sequential elements, low-power cells, level shifters, ESD-protected I/O interfaces, and process-specific implementation libraries optimized for leading foundries.
This catalog enables semiconductor engineers to evaluate and compare Foundation Library IP solutions from multiple vendors based on process node support, PPA (Power, Performance, Area) characteristics, library characterization quality, voltage domains, reliability requirements, and integration with modern EDA design flows.
Whether targeting AI accelerators, automotive SoCs, networking devices, wireless chipsets, or high-performance computing applications, engineers can identify the Foundation Library IP best suited to their technology, performance, and manufacturing requirements.
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as s…
Standard Cell Library in TSMC (12nm~180nm)
M31 provides a variety of cell libraries, including Ultra-High Density Standard Cell Library (HDSC), General Purpose Standard Cel…
General Purpose I/O (GPIO) in TSMC(12nm,16nm,22nm, 28nm, 40nm, 90nm BCD+, 152nm BCD, 180nm BCD)
GPIO is a general-purpose input/output unit that provides basic input/output functionalities.
1.8V General Purpose Staggered I/O Pad Set
The 1.8V GPIO library provides general purpose bidirectional I/O cells.
3.3V Wide-Range General Purpose Inline I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …
1.8V General Purpose I/O Staggered Pad Set
The 1.8V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …
The Synopsys Duet Packages of Embedded Memories and Logic Libraries, part of Synopsys Foundation IP portfolio, offer an integrate…
The SMBus library provides open-drain bi-directional I/O cells designed for the High-Power SMBus two-line interface.
The ESD Protection library provides ESD protection components.
6 track High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME HD provides the best trade-off between area and power achieved from an cell design enabling 6-track cells.
Over-voltage Protection Module to handle direct connection of voltage regulators to a 5V battery using standard IO devices
Ultra-low leakage I/O Library in TSMC 22nm
A TSMC 22nm Wirebond I/O Library with ultra-low leakage 1.8V GPIO, 1.8V I2C ODIO, 1.8V analog cell and associated ESD.
5V I/O and ESD in TSMC 12nm FFC/FFC+
A 5V Library for Generic I/O and ESD Applications TSMC 12NM FFC/FFC+ process.
The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface.
The CML library provides a differential current mode logic clock driver to support REFCLK signaling in PCIe applications along wi…
The ONFI 4.1 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage ref…
The 1.8V Fault-Tolerant General Purpose I/O library provides a 3.3V tolerant programmable, bidirectional I/O that give the system…
1.8V General Purpose I/O Inline Pad Set
The 1.8V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …
3.3V Wide-Range General Purpose Staggered I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …
1.8V 3.3V Tolerant General Purpose IO
The 1.8V GPIO 3VT library provides general purpose bidirectional I/O cells that are both fault tolerant and 3.3V tolerant.