ESD Protection
The ESD Protection library provides ESD protection components.
Overview
The ESD Protection library provides ESD protection components. In addition to core-placeable ESD protection cells, discrete components (RF diodes and SCR’s) are provided to enable construction of a custom ESD protection solution.
This library is compatible with all 7nm library offerings.
Key features
- ESD Protection:
- JEDEC compliant
- 2KV ESD Human Body Model (HBM)
- 500 V ESD Charge Device Model (CDM)
- Latch-up Immunity:
- JEDEC compliant
- Tested to I-Test criteria of ± 100mA @ 125°C
- JEDEC compliant
- JEDEC compliant
What’s Included?
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 7nm | N7+ | Silicon Proven |
Specifications
Identity
Provider
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Frequently asked questions about ESD Protection Library IP cores
What is ESD Protection?
ESD Protection is a ESD Protection IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this ESD Protection?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ESD Protection IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.