What is SMBus IO Pad Set?
SMBus IO Pad Set is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Vendor:
Aragio Solutions
Category:
GPIO
SMBus IO Pad Set
The SMBus library provides open-drain bi-directional I/O cells designed for the High-Power SMBus two-line interface.
Overview
The SMBus library provides open-drain bi-directional I/O cells designed for the High-Power SMBus two-line interface. It is compliant with the Rev 3.1 of the SMBus specification.
The design supports the Sm, Fm and Fm+ modes of operation at the SMBus operating voltage (VDDP) of either extended range 3.3V or standard 1.8V logic.
This 7nm library is available in a staggered flip chip implementation.
To utilize these cells in the pad ring, an additional library is required – 1.8V Support: Power. That library contains the power cells, the POC cell, and a rail splitter to isolate the SMBus cells in their own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
ESD Protection:
? JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)
Latch-up Immunity:
? JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C
The design supports the Sm, Fm and Fm+ modes of operation at the SMBus operating voltage (VDDP) of either extended range 3.3V or standard 1.8V logic.
This 7nm library is available in a staggered flip chip implementation.
To utilize these cells in the pad ring, an additional library is required – 1.8V Support: Power. That library contains the power cells, the POC cell, and a rail splitter to isolate the SMBus cells in their own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
ESD Protection:
? JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)
Latch-up Immunity:
? JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C
Key features
- • Supported I2C operating modes:
- o Standard-mode (Sm) – 10 to 100 kbps data rate
- o Fast mode (Fm) – 10 to 400 kbps data rate
- o Fast mode (Fm+) – 10 kbps to 1 Mbps data rate
- • Open drain operation only (floating NWELL with PMOS used for ESD protection only)
- • Built-in output slew rate control to meet I2C Tof minimum of (20 x VDDP/5.5V) ns
- • Output enable
- • Receiver enable
- • ESD protection is accomplished with an SCR (no diode to the positive power supply)
- • Standard LVCMOS compatible inputs with Schmitt trigger (hysteresis) option
- • Power-on sequencing independent design with Power-On Control
- • DVDD = 1.62V to 1.98V
- • Pad VDDP (power supply reference for Output)
- o 2.7V to 3.63V – extended range 3.3V
- o 1.62V to 1.98V – standard range 1.8V
- • The circuit consumes no DC supply current in the static state
- An open-drain design, this cell requires an external pull-up resistor to a high voltage power supply. The pull-up power supply (VDDP) can be 3.63V maximum, independent of the I/O cell power supply (DVDD). In a 1.8V SMBus application, VDDP can track DVDD but it is not necessary.
- Vertical-only (_V) and and horizontal-only (_H) variants provided.
What’s Included?
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 7nm | N7+ | Silicon Proven |
Specifications
Identity
Part Number
RGO_TSMC07_18V33_7FF_20C_SMB
Vendor
Aragio Solutions
Type
Silicon IP
Provider
HQ:
USA
Frequently asked questions about GPIO Pad Library IP cores
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.