What is ONFI_4 IO Pad Set?
ONFI_4 IO Pad Set is a High-Speed IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Vendor:
Aragio Solutions
Category:
High-Speed
ONFI_4 IO Pad Set
The ONFI 4.1 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage ref…
Overview
The ONFI 4.1 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to support both single-ended and differential ONFI 4.1 signaling. This library also meets the requirements for ONFI 3.0 & Toggle 2.0 signaling. Also included is a full complement of power, spacer, and adapter cells to assemble a complete pad ring by abutment. An included rail splitter allows isolated ONFI domains to be placed in the same pad ring with other power domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.
The ONFI 4.1 I/O library supports all impedance modes defined in the ONFI 4.1 specification and features fast and precise calibration, low power consumption, area-efficient design, and easy integration into the physical layer (PHY).
This 7nm library is available in a staggered flip chip implementation.
ESD Protection:
? JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)
Latch-up Immunity:
? JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C
The ONFI 4.1 I/O library supports all impedance modes defined in the ONFI 4.1 specification and features fast and precise calibration, low power consumption, area-efficient design, and easy integration into the physical layer (PHY).
This 7nm library is available in a staggered flip chip implementation.
ESD Protection:
? JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)
Latch-up Immunity:
? JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C
Key features
- ONFI Single-Ended Driver / Receiver Features:
- ? Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
- o ODT Rtt = 30? / 50? / 75? / 100? / 150?
- o ZOUT = 18? / 25? / 35? / 50?
- o Off state – Z / pull-up / pull-down / bus keeper
- ? Receiver – single-ended and pseudo-differential outputs
- ? Powered by 1.2V / 1.8V I/O and 0.8V core supplies
- ? Maximum operating frequency – 400 MHz
- ONFI Differential Clock Driver / Receiver Features:
- ? Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
- o ODT Rtt = 30? / 50? / 75? / 100? / 150?
- o ZOUT = 18? / 25? / 35? / 50?
- o Off state – Z / pull-up / pull-down / bus keeper
- ? Receiver – single-ended and true differential outputs
- ? Powered by 1.2V / 1.8V I/O and 0.8V core supplies
- ? Maximum operating frequency – 400 MHz
What’s Included?
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 7nm | N7+ | Silicon Proven |
Specifications
Identity
Part Number
RGO_TSMC07_18V18_7FF_20C_ONFI_4_1
Vendor
Aragio Solutions
Type
Silicon IP
Provider
HQ:
USA
Frequently asked questions about High-Speed I/O Pad IP
How should engineers evaluate this High-Speed?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.