What is 1.8V 3.3V Tolerant General Purpose IO?
1.8V 3.3V Tolerant General Purpose IO is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Vendor:
Aragio Solutions
Category:
GPIO
1.8V 3.3V Tolerant General Purpose IO
The 1.8V GPIO 3VT library provides general purpose bidirectional I/O cells that are both fault tolerant and 3.3V tolerant.
Overview
The 1.8V GPIO 3VT library provides general purpose bidirectional I/O cells that are both fault tolerant and 3.3V tolerant. These programmable, multi-voltage I/O’s give the system designer the flexibility to design to a wide range of performance targets.
These libraries are offered at both 16nm and a 12nm shrink. They
are available in a staggered CUP wire bond implementation with a flip chip option.
To design a functional I/O power domain with these cells, an additional library is required – 1.8V Support: Power. That library contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
These libraries are offered at both 16nm and a 12nm shrink. They
are available in a staggered CUP wire bond implementation with a flip chip option.
To design a functional I/O power domain with these cells, an additional library is required – 1.8V Support: Power. That library contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
Key features
- • High performance, programmable general purpose I/O cell
- 3.3V tolerant only @ VDVDD = 1.8V
- Fault tolerant @ PAD = 3.3V
- • Staggered CUP wire bond implementation with flip chip option
- • Power supply sequencing independent design with Power-On Control
- • Robust ESD Protection
- 2KV ESD Human Body Model (HBM)
- ? Compliant with ANSI/ESDA/JEDEC JS-001-2017 (December 8, 2016)
- 500V ESD Charge Device Model (CDM)
- ? Compliant with JESD22-C101F (October 2013)
- • Latch-up Immunity
- Compliant with JESD78E (April 2016)
- Tested using I-Test criteria of ±100mA at maximum ambient temperature of +125°C.
What’s Included?
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 12nm | FFC | Silicon Proven |
Specifications
Identity
Part Number
RGO_TSMC12_18V18_FFC_LL_20C_3VT
Vendor
Aragio Solutions
Type
Silicon IP
Provider
HQ:
USA
Frequently asked questions about GPIO Pad Library IP cores
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.