DVB-S2X LDPC/BCH Decoder IP (Silicon Proven)
The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single outpu…
- Channel Coding
- Silicon Proven
- Immediate
- Certified
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
DVB-S2X LDPC/BCH Decoder IP (Silicon Proven)
The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single outpu…
The Fast sort IP core is a AXI-compatible digital hardware block with internal data sorting algorithm.
2K TicoRAW Encoder / Decoder for RAW CFA sensor data compression
Engineered at intoPIX, TicoRAW is an , lossless quality, low-power, low-memory and line-based image processing and compression te…
8K TicoRAW Encoder / Decoder for RAW CFA sensor data compression
Engineered at intoPIX, TicoRAW is an , lossless quality, low-power, low-memory and line-based image processing and compression te…
4K TicoRAW Encoder / Decoder for RAW CFA sensor data compression
Engineered at intoPIX, TicoRAW is an , lossless quality, low-power, low-memory and line-based image processing and compression te…
Our Processor for high embedded performance with RISC-V instruction-set compatibility, permit users to grasp the rich ecosystem o…
The AWGN Channel IP is a noise generator capable of processing up to a maximum of 512 symbols in parallel.
8-Bit Microcontroller Based on the W65C02
The W65C02i1M08SC Microprocessor Datasheet is for MyMENSCH™ Rev-A.
5G NR is the mobile broadband standard of the 5th generation.
Generic Polar FEC Encoder and Decoder
Polar codes are a trending family of forward error correction codes currently gaining a place in the realm of digital communicati…
A Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems.
Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
The H50 is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large addres…
The Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying inp…
CCSDS AR4JA LDPC Encoder & Decoder
The CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard.
RISC-V processor - 32 bit, 5-stage pipeline
The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requ…
LTE and LTE (LTE-A) are the mobile broadband standard of the 4th generation.
Single precision fixed-size streaming floating-point FFT
This FFT circuit employs unique architectural characteristics providing functionality and capabilities not possible with other FF…
CCSDS LDPC Encoder and Decoder
The CCSDS LDPC IP cores support the LDPC coding scheme as defined by the CCSDS standard.
DVB-S2 (Digital Video Broadcast – Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmi…
DVB-CID (Digital Video Broadcast - Carrier Identification System) is an ETSI standard for interference prevention within digital …