Discover CPU and Microcontroller IP for embedded processing, real-time control, and general-purpose computation in semiconductor designs. This category includes processor IP used in SoCs, ASICs, and embedded platforms requiring software programmability, deterministic control, and scalable compute performance.
Compare CPU and Microcontroller IP by ISA, bit width, safety support, performance level, memory architecture, debug features, ecosystem maturity, and target applications. These IP cores are widely used in automotive, industrial, IoT, consumer, and communication chips.
ARC HS34 32-bit processor core, ARC V2 ISA, for embedded applications
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
The ARC-V™ RPX-100 series processors feature a dual-issue, 64-bit superscalar architecture for use in high performance applicatio…
ARC-V RHX Series Functional Safety Processor IP
The ARC-V™ RHX-110-FS, RHX-115-FS, RHX-110V-FS, and RHX-115V-FS functional safety processors simplify development of high-perform…
The ARC-V™ RHX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where real-tim…
ARC Data Fusion Voice/Speech Option
IoT applications increasingly require sensing capabilities that extend beyond what traditional sensors provide.
32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification.
Neoverse Compute Subsystems N2 (CSS N2)
Neoverse CSS N2: The Arm Neoverse N2 Platform, Delivered to Partners as a Verified, Performance-Validated Customizable Subsystem …
A CPU Foundation for the AI-Driven Datacenter The Arm Neoverse V3 CPU is built to deliver maximum performance for cloud applicati…
Optimal Performance and Power Efficiency for Hyperscale, Telecom, Networking, and Infrastructure Edge Devices The Arm Neoverse N3…
32-bit RISC-V microcontroller.
64-bit RISC-V embedded core with in-order single issue pipeline
64-bit RISC-V embedded core with in-order single issue pipeline.
32-bit RISC-V embedded core with in-order single issue pipeline
32-bit RISC-V embedded core with in-order single issue pipeline.
The second-generation high-performance RISC-V CPU delivers a major leap in compute capability, designed for deployment across dat…
Low-Power Deeply Embedded RISC-V Processor
The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core.
Infrastructure for Next-Generation Throughput Demands The Neoverse E1 processor is a new class of efficient CPU technology design…
A Revolution in High Performance Computing The Neoverse V1 CPU is designed to deliver per-core performance on demanding HPC, HPC …
Industry- Performance and Power Efficiency for Cloud-to-Edge Infrastructure Our first Armv9 infrastructure CPU, Neoverse N2 offer…
Ultra-Low-Power Deeply Embedded RISC-V Processor
The BA51 is a configurable, low-power, deeply embedded RISC-V processor IP core.
H8SX CPU subsystem (H8SX C3000) IP
H8SX is a high speed 32-bit CPU, which is upward-compatible with H8/300, H8/300H and H8S CPUs on an object level.
H8S CPU subsystem (H8S C200) IP
H8S is a high speed 16-bit CPU with an internal 32-bit architecture, which is upward-compatible with H8/300 and H8/300H CPUs on a…