SiFive 2nd Generation Intelligence Family Introduction
SiFive Co-Founder and Chief Architect, Krste Asanovic, introduces SiFive's latest RISC-V based AI accelerator IP designed to enable customers to build the next generation of edge AI acceleration into devices from the far edge to the cloud.
Related Semiconductor IP
- Multi-core capable 32-bit RISC-V CPU with vector extensions
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 8-stage dual issue, in-order, superscalar processor with dual vector processing units (1024-bit VLEN/512-bit DLEN)
- Multi-core capable RISC-V processor with vector extensions
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
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