Tackling Network-on-Chip (NoC) Scaling Challenges with a System-technology Co-optimization Approach
In the rapidly evolving field of cloud computing, maximizing computational resources within physical and power constraints has become paramount....
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NoC Semiconductor IP News & Insights
Follow the latest news, technical articles, expert perspectives and ecosystem updates related to NoC and semiconductor IP design.
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282 results about NoC
2024 Set The Stage For NoC Interconnect Innovations In SoC Design
What a year it’s been for Arteris! Reflecting on 2024, the company achieved exciting milestones and breakthroughs that pushed the boundaries of system-on-chip...
Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling
Andy Nightingale, VP Product Management & Marketing at Arteris, spoke to EE Journal’s Amelia Dalton on the fish fry podcast.
Scaling AI Chip Design With NoC Soft Tiling
Tiling is about repeating modular units within the same chip to enhance scalability and efficiency; chiplets involve combining different silicon...
Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning
A new trend is emerging in the design of high-end, multi-billion-transistor system-on-chip (SoC) devices. Referred to as “NoC tiling,” this evolutionary...
Tenstorrent Expands Deployment of Arteris’ Network-on-Chip IP to Next-Generation of Chiplet-Based AI Solutions
Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced Tenstorrent has licensed...
Arteris Network-on-Chip Tiling Innovation Accelerates Semiconductor Designs for AI Applications
Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced an innovative evolution...
SignatureIP Networks-on-Chips (NoCs) to Accelerate RISC-V Designs
SignatureIP, the pioneer of next generation interconnect and interface solutions, announces that its Networks-on-Chips (NoCs) provide the necessary...
NoCs and the transition to multi-die systems using chiplets
Monolithic dies have long been used in integrated circuit (IC) design, offering a compact and efficient solution for building application-specific...
SignatureIP Makes Network-on-Chip (NoC) Design Widely Accessible with Cloud-Based iNoCulator™ Platform
Available at iNoCulator.ai, it is the first cloud-based platform for design of a Network on Chip (NoC). A NoC provides the interconnect infrastructure...
Why verification matters in network-on-chip (NoC) design
In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that...
Navigating Integration Challenges for the RISC-V Ecosystem with Networks-on-Chips (NoCs)
Frank Schirrmeister, Arteris
About NoC in semiconductor IP
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