Automating NoC Design Masters SoC Complexity
By Sally Ward-Foxton, EETimes | May 21, 2025
Today, we’re diving into the critical role of network-on-chip (NoC) design in modern system-on-chip (SoC) architectures. Designing efficient interconnects has become a major challenge as SoCs grow more complex, especially with the increasing integration of AI workloads. NoCs now account for a significant portion of silicon area, making it essential to get them right. Michal Siwinski, Chief Marketing Officer at Arteris, will join us in discussing how FlexGen, their network-on-chip IP technology, is revolutionizing NoC design through automation. We’ll explore why this is crucial for today’s chips, how it addresses the growing demands of AI, and what the future holds for NoC technology.
To read the full article, click here
Related Semiconductor IP
- FlexGen Smart Network-on-Chip (NoC) IP
- FlexNoC Interconnect IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- NoC Interconnect IP Generator
- AXI NoC Non-Coherent Mesh
Related News
- Andes and Arculus System Collaborate to Integrate iPROfiler™ into AndeSysC, Expanding Virtual Platform Support for RISC-V SoC Design
- Aion Silicon Expands Barcelona Design Center to Meet Surging Demand for ASIC and SoC Solutions
- IObundle Releases Open-Source UART16550 Core for FPGA SoC Design
- AMI Announces a Shift-Left Initiative to De-Risk SoC Development for Arm Total Design in Collaboration with Arm and Synopsys
Latest News
- Weebit Nano Q1 FY27 Activities Update
- INTERA Launches EAGLE Cognit, Bringing Ultra-Low-Power Near-Memory AI Acceleration to Next-Generation Edge Devices
- AeroTSN-EP in Action: SOC-E Brings Live Aerospace TSN Demonstration to A&D TSN Summit 2026
- Agnisys and Axiomise Collaborate to Accelerate NoC Design and Formal Sign-off
- TSMC Reports Third Quarter EPS of NT$29.43