NoCs and the transition to multi-die systems using chiplets
Monolithic dies have long been used in integrated circuit (IC) design, offering a compact and efficient solution for building application-specific...
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NoC Semiconductor IP News & Insights
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286 results about NoC
SignatureIP Makes Network-on-Chip (NoC) Design Widely Accessible with Cloud-Based iNoCulator™ Platform
Available at iNoCulator.ai, it is the first cloud-based platform for design of a Network on Chip (NoC). A NoC provides the interconnect infrastructure...
Why verification matters in network-on-chip (NoC) design
In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that...
Navigating Integration Challenges for the RISC-V Ecosystem with Networks-on-Chips (NoCs)
Frank Schirrmeister, Arteris
SignatureIP's iNoCulator Tool - a Simple-to-use tool for Complex SoCs
A Network-on-chip (NoC) is a network inside a System-on-chip (SoC) that connects to all IO, Compute and Storage devices. In addition to its networking...
SignatureIP launches its new iNoCulator NoC configuration tool with a free trial offer
SignatureIP, the pioneer of next generation NoC tools, has launched its new iNoCulator™ NoC configuration tool with a free trial period of two weeks...
SoC design: When a network-on-chip meets cache coherency
Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially...
Extending network-on-chip (NoC) technology to chiplets
The majority of today’s ICs employ some form of NoC, but how will the NoC-based chiplets communicate with each other?
Fraunhofer IESE Partners With Arteris To Accelerate Advanced Network-on-chip Architecture Development for AI/ML Applications
Combining FlexNoC and Ncore from Arteris with Fraunhofer IESE DRAMSys4.0 enables customers to improve performance, reduce cost and accelerate the...
Accelerating RISC-V development with network-on-chip IP
In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single...
Optimize SoC Design with a Network-on-Chip Strategy
Utilizing physically aware interconnect IP from trusted third-party vendors can reduce design time and increase productivity.
Network-on-chip (NoC) interconnect topologies explained
Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks. Each IP block may have its own data width and clock...
About NoC in semiconductor IP
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