Chiplets Semiconductor IP News & Insights

Credo Announces 3.2Tbps XSR-Enabled High-Speed Connectivity Chiplet with 112Gbps Lane Rates

Credo today announced the production availability of Nutcracker, the industry's first low-power 3.2Tbps retimer XSR-enabled high-speed connectivity...

Designing chiplet and co-packaged optics architectures with 112G XSR SerDes

ARM pushes chiplets and 3D packaging for Neoverse chips

ARM has launched an enhanced mesh interconnect IP for its high performance Neoverse processor cores that enables more use of chiplets and 3D packaging.

OpenFive Launches Die-to-Die Interface Solution for Chiplet Ecosystem

OpenFive, the leading provider of customizable, silicon-focused solutions with differentiated IP, today announced the launch of a Die-to-Die (D2D)...

More than Chiplets | Facebook Enters the Fray

Our chiplet discussion left off with the historical perspective that “this isn’t new.” Heterogenous integration, system-in-package (SiP) and the...

AMD, TSMC & Imec Show Their Chiplet Playbooks at ISSCC

A lot has been said about the shift from a system-on-chip integration of functionality to a technology integrating each IP block as a physically...

Apple M1 Processor, Passing on the Chiplets

Recent angry comments to EE Times‘ interview with Intel’s Ramune Nagisetty disparaged the current heterogenous integration and chiplet discussions...

OpenFive Enhances Differentiated IP Portfolio with Die-to-Die Interface Controllers for HPC and Chiplet Markets

OpenFive, the leading provider of customizable, silicon-focused solutions with differentiated IP, today announced the launch of a new Die-to-Die...

CHIPS Alliance Announces AIB 2.0 Draft Specification to Accelerate Design of Open Source Chiplets

CHIPS Alliance today announced that it has released the Advanced Interface Bus (AIB) version 2.0 draft specification on GitHub. The AIB standard...

Rambus Delivers 112G XSR/USR PHY on TSMC 7nm Process for Chiplets and Co-Packaged Optics in Networking and Data Center

Rambus Inc., a premier silicon IP and chip provider making data faster and safer, today announced it has expanded its portfolio of high-speed interface...

CEA-Leti Presents High-Performance Processor Breakthrough With Active Interposer and 3D Stacked Chiplets at ISSCC 2020

Leti and List, institutes of CEA-Tech, reported a high-performance processor breakthrough using an active interposer as a modular and energy- efficient...

Achronix, Cisco, Facebook, Netronome, NXP and zGlue Collaborate on Proof-of-Concept for Chiplet Solutions as Part of OCP ODSA Subproject

Achronix, Cisco, Facebook, Netronome, NXP and zGlue shared details on the progress of their collaboration to validate technology and business opportunities...