Designing chiplet and co-packaged optics architectures with 112G XSR SerDes

By Rambus Inc.

May 19, 2021

Suresh Andani, senior director of product marketing at Rambus, has written an article for Semiconductor Engineering that takes an in-depth look at how 112G XSR SerDes can be used to optimally design chiplet and co-packaged optics architectures.

As Andani notes, conventional chip designs are struggling to achieve the scalability, as well as power, performance, and area (PPA) that are expected of leading-edge designs.

“With the slowing of Moore’s Law, high complexity ASICs increasingly bump up against reticle limits. The demise of Dennard scaling means power consumption is [also] a growing challenge,” he explains. “In this context, disaggregated architectures such as chiplets or co-packaged optics (CPO) become truly viable alternatives to the traditional monolithic SoC scaling approach.”

To read the full article, click here