On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
By Mehdi Elahi 1, Mohamed R. Elshamy 2, Abdel-Hameed A. Badawy 2 and Ahmad Patooghy 1
1 North Carolina A&T State University
2 New Mexico State University

Abstract
3D-stacked High Bandwidth Memory (HBM) architectures provide high-performance memory interactions to address the well-known performance challenge, namely the memory wall. However, these architectures are susceptible to thermal vulnerabilities due to the inherent vertical adjacency that occurs during the manufacturing process of HBM architectures. We anticipate that adversaries may exploit the intense vertical and lateral adjacency to design and develop thermal performance degradation attacks on the memory banks that host data/instructions from victim applications. In such attacks, the adversary manages to inject short and intense heat pulses from vertically and/or laterally adjacent memory banks, creating a convergent thermal wave that maximizes impact and delays the victim application from accessing its data/instructions. As the attacking application does not access any out-of-range memory locations, it can bypass both design-time security tests and the operating system's memory management policies. In other words, since the attack mimics legitimate workloads, it will be challenging to detect.
Keywords: 3D-Stacked Memory, HBM, Thermal Attack, Thermal Coupling, Security
To read the full article, click here
Related Semiconductor IP
- HBM Memory Controller
- HBM Memory Model
- HBM DFI Verification IP
- HBM 4 Verification IP
- HBM Synthesizable Transactor
Related Articles
- Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips
- SoCs: DSP World, Cores -> New DSP architectures work harder
- Processor forum examines embedded cache, architectures
- What is the impact of streaming data on SoC architectures?
Latest Articles
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
- Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains