HBM DFI Synthesizable Transactor

HBM DFI Synthesizable Transactor provides a smart way to verify the HBM DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's HBM DFI Synthesizable Transactor is fully compliant with standard DFI version 4.0 or 5.0 Specifications and provides the following features.

• Compliant with DFI version 4.0 or 5.0 Specifications.
• Supports HBM devices compliant with JEDEC HBM DRAM Standard JESD235, JESD235A, JESD235B and JESD235C.
• Supports all Interface Groups.
• Supports Write Transactions with Data mask
• Supports DRAM Clock disabling feature.
• Supports Data bit enable/disable feature.
• Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
• Supports frequency change protocol.
• Supports Low power control features.
• Supports Error signaling.
• Supports DFI Read/Write Chip Select.
• Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
• Protocol checker fully compliant with DFI 4.0 or 5.0 Specifications.

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

• Synthesizable transactors
• Complete regression suite containing all the HBM DFI testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and function's used in verification env
• Documentation contains User's Guide and Release notes