Vendor: SmartDV Category: HBM

HBM DFI Synthesizable Transactor

HBM DFI Synthesizable Transactor provides a smart way to verify the HBM DFI component of a SOC or a ASIC in Emulator or FPGA plat…

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Overview

HBM DFI Synthesizable Transactor provides a smart way to verify the HBM DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's HBM DFI Synthesizable Transactor is fully compliant with standard DFI version 4.0 or 5.0 Specifications and provides the following features.

Key features

  • Compliant with DFI version 4.0 or 5.0 Specifications.
  • Supports HBM devices compliant with JEDEC HBM DRAM Standard JESD235, JESD235A, JESD235B and JESD235C.
  • Supports all Interface Groups.
  • Supports Write Transactions with Data mask
  • Supports DRAM Clock disabling feature.
  • Supports Data bit enable/disable feature.
  • Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
  • Supports frequency change protocol.
  • Supports Low power control features.
  • Supports Error signaling.
  • Supports DFI Read/Write Chip Select.
  • Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
  • Protocol checker fully compliant with DFI 4.0 or 5.0 Specifications.

Block Diagram

HBM DFI Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the HBM DFI testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
HBM DFI Transactor
Vendor
SmartDV
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about HBM IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about HBM Interface IP

What is HBM DFI Synthesizable Transactor?

HBM DFI Synthesizable Transactor is a HBM IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this HBM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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