Retiming USB4 over USB-C
Brian Holden, Kandou Bus
embedded.com (January 15, 2021)
The USB-C connector is the one connector to rule them all. It has wonderful flexibility in its definition and has been widely adopted across different interconnects. That flexibility and diversity of use are also the source of many difficulties when trying to retime the signals that run over it, particularly in active cables. A key source of those difficulties for retimers are the many interactions between all of the options and modes that USB-C supports.
USB-C supports USB, Thunderbolt, DisplayPort, HDMI and MHL as well as other emerging protocols via a series of alternative or “Alt” modes. Each has its own protocol and physical and layers that have to be dealt with separately by a retimer. They were defined by different groups at different times and for strongly different purposes. The protocol layers are different from each other. The physical layers were also defined in disparate ways with differing rates and significant backward compatibility modes and constraints. It is a feat of clever engineering that they could be fit together and operate over one connector definition.
To read the full article, click here
Related Semiconductor IP
- USB-C 3.1/DP TX PHY in GF (22nm)
- USB-C 3.1 DP/TX PHY ebdaux in TSMC (N5, N3E)
- USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A)
- USB-C 3.1/DP TX PHY in Samsung (14nm, 11nm, 5nm)
- USB-C 3.1/DP TX PHY in TSMC (16nm, 12nm, N7, N6)
Related Articles
- MEMS market to grow 75-87% over five-year period, says report
- SoCs: DSP World, Cores -> Multiservices over broadband cable
- Embedded Systems : Voice over IP
- At Last: Wait Is Over For Bluetooth
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection