PCI Express goes everywhere
Jag Bolaria, The Linley Group
EE Times (07/18/2008 3:00 PM EDT)
PCI Express HAS become the leading chip interconnect, dominating in servers, storage systems and PCs. PC economies of scale have spurred processor and ASIC suppliers to integrate PCIe interfaces. In turn, those chips are driving PCI Express into embedded systems and networking.
The Linley Group estimates last year's market for PCI Express connectivity products, primarily bridges and switches, at $55 million. Most of the revenue was from the server and storage segments.
We expect the connectivity market to exceed $195 million by 2011. Much of the growth will come from communications and embedded. A breakout of this market is detailed in The Linley Group report "A Guide to High-Speed Interconnects."
PCIe has evolved from the 2.5-Gbit/second serial data rate of the original spec (Gen1) to 5 Gbits/s in v2.0 (Gen2). Multigigabit-rate requirements for networking and the adoption of blade servers are driving the need for Gen2.
Requirements in server, storage, embedded and networking applications differ, however, from the standard PCIe configuration in PCs. PC applications focus on low cost, with four-layer boards and small trace lengths.
EE Times (07/18/2008 3:00 PM EDT)
PCI Express HAS become the leading chip interconnect, dominating in servers, storage systems and PCs. PC economies of scale have spurred processor and ASIC suppliers to integrate PCIe interfaces. In turn, those chips are driving PCI Express into embedded systems and networking.
The Linley Group estimates last year's market for PCI Express connectivity products, primarily bridges and switches, at $55 million. Most of the revenue was from the server and storage segments.
We expect the connectivity market to exceed $195 million by 2011. Much of the growth will come from communications and embedded. A breakout of this market is detailed in The Linley Group report "A Guide to High-Speed Interconnects."
PCIe has evolved from the 2.5-Gbit/second serial data rate of the original spec (Gen1) to 5 Gbits/s in v2.0 (Gen2). Multigigabit-rate requirements for networking and the adoption of blade servers are driving the need for Gen2.
Requirements in server, storage, embedded and networking applications differ, however, from the standard PCIe configuration in PCs. PC applications focus on low cost, with four-layer boards and small trace lengths.
To read the full article, click here
Related Semiconductor IP
- PCIe - PCI Express Controller
- Scalable Switch Intel® FPGA IP for PCI Express
- Multichannel DMA Intel FPGA IP for PCI Express*
- PCI Express Gen5 SERDES PHY on Samsung 8LPP
- PCI Express Gen4 SERDES PHY on Samsung 7LPP
Related Articles
- How HyperTransport and PCI Express complement each other
- Advanced switching boosts PCI Express
- Compatibility issue slows PCI Express
- With StarFabric as an on-ramp, the PCI Express Advanced Switching is ready
Latest Articles
- Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
- TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
- Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
- A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
- ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits