Vendor: Zero ASIC Category: eFPGA

eFPGA on GlobalFoundries GF12LPP

GF12LPP process node; 4.8 mm X 4.8 mm; 51K LUTs

GlobalFoundries 12nm LP+ Available on request View all specifications

Overview

The Z1015 standard eFPGA architecture has been ported to the GlobalFoundries GF12LPP process. Released to general availability in June 2026, the Z1015 is the largest Platypus eFPGA core to date and is the hardened IP at the heart of Zero ASIC’s heterogeneous FPGA chiplet. See the launch announcement for details.

Process LUTs Regs I/O DSPs BRAM Width Height
GF12LPP 51,840 63,944 12,112 180 180 4.8mm 4.8mm

 

Key features

  • GF12LPP process node
  • 4.8 mm X 4.8 mm
  • 51K LUTs
  • 63K registers
  • 3Mb BRAM (180x16kbit)
  • 180 DSPs
  • 12K GPIO pins
  • 4 global clocks
  • APB programming interface
  • 100% open and standardized FPGA architectures
  • 100% open source FPGA bitstream formats
  • 100% open source FPGA development tools

Block Diagram

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Benefits

Platypus is the ONLY commercial eFPGA product backed up by:

  • 100% open and standardized FPGA architectures
  • 100% open source FPGA bitstream formats
  • 100% open source FPGA development tools

Applications

  • FPGA/CPLD/ASIC obsolescence
  • hardware security
  • I/O peripherals
  • interface bridges
  • motor control
  • signal muxing
  • power management
  • glue logic

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP+ Available on request

Specifications

Identity

Part Number
Z1015-GF12LPP
Vendor
Zero ASIC
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Zero ASIC
HQ: USA

Learn more about eFPGA IP core

Tardigrade, an ASIC synthesis engine designed for AI

Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced the release of Tardigrade™, a state of the art ASIC synthesis engine designed for the age of AI driven chip design.

Zero ASIC releases Platypus 12nm eFPGA product

The Z1015 IP core has already been used by the Zero ASIC chiplet design team to develop a state of the art heterogeneous FPGA chiplet and is now being offered to external customers.

Frequently asked questions about eFPGA IP cores

What is eFPGA on GlobalFoundries GF12LPP?

eFPGA on GlobalFoundries GF12LPP is a eFPGA IP core from Zero ASIC listed on Semi IP Hub. It is listed with support for globalfoundries Available on request.

How should engineers evaluate this eFPGA?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this eFPGA IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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