Understand LTE-A Release 12 transmitter architecture: Part 1
Damian Anzaldo, Maxim Integrated
EDN (March 06, 2015)
This two-part article series reviews new developments in the Fourth Generation Long Term Evolution (4G-LTE) cellular standard. The articles explore LTE-Advanced (LTE-A) Release-12 (Rel-12) features and their impact on eNodeB radio frequency (RF) transmitters. The articles reveal how analog integration can overcome design challenges arising from the latest 4G developments. A Glossary of Technical Terms is appended to the end of each article to help with acronyms.
This article examines market forces driving global adoption of the LTE standard and trends in 4G radio access technology. Topics include carrier aggregation (CA), spatial multiplexing, and active antenna systems (AAS). Part 2 of this series explores the analog integration challenges in 4G base stations. Rel-12 features such as wideband downlink CA, downlink multiple-input multiple-out (MIMO) spatial multiplexing, and AAS with embedded RF, present new design challenges in next-generation eNodeB radios. A disruptive bits-to-RF solution can help engineers shape alternative radio transmitter architectures. The discussion focuses on novel RF digital-to-analog converter (RF-DAC) technology that yields a single-chip, wideband RF transmitter solution.
To read the full article, click here
Related Semiconductor IP
- Viterbi decoder for 3GPP WCDMA and 3GPP-LTE
- LTE Turbo decoder
- 3GPP LTE Fast Fourier Transform (LTE-FFT)
- LTE Turbo Decoder
- 3GPP LTE DL Channel Encoder
Related Articles
- LTE-A Release 12 transmitter architecture: analog integration
- Reconfiguring Design -> C-based architecture assembly supports custom design
- High-Performance DSPs -> Processor boards: Architecture drives performance
- Opto-electronics -> High-density fiber-optic modules eye next-gen switching architecture
Latest Articles
- FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity
- MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
- Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs
- SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment
- Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing