Efficient I2C Bus debug using Mixed Signal Oscilloscopes
Dave Pereles, Tektronix
embedded.com (October 7, 2012)
Version 4.0 of the Inter-IC (I2C) bus is widely used in embedded system designs, and has been used for communications and control applications in thousands of integrated circuits.
What’s also still widely used is manual measurement and debug, in part because engineers assume that since I2C has been around for a long time, there’s little to go wrong. The trouble comes when there’s a need to trigger bus commands using manual decode.
I2, I2C, or “I squared C”, stands for Inter-Integrated Circuit. It was originally developed by Philips Semiconductor in the early 1980s to provide a low-cost way of connecting controllers to peripheral chips, and has since evolved into a worldwide standard for communication between devices in embedded systems.
The simple two-wire design has found its way into an extensive cross section of chips including I/O, A/Ds, D/As, temperature sensors, microcontrollers and microprocessors from numerous leading chipmakers including Analog Devices, Atmel, Cyprus, Freescale, Infineon, Intel, Maxim, Microchip, NXP, Silicon Labs, ST Microelectronics, Texas Instruments, Xicor, and many others.
To read the full article, click here
Related Semiconductor IP
- I2C protocol Controller
- I2C - Verifies I2C communication, ensuring protocol compliance and error-free data transfer
- I2C Master and Slave
- I2C Verification IP
- I2C Synthesizable Transactor
Related Articles
- Analog & Mixed Signal IC Debug: A high precision ADC application
- Modeling and Verification of Mixed Signal IP using SystemVerilog in Virtuoso and NCsim
- Mixed Signal SoC Applications
- It Takes tools to Raise a Programmable Mixed Signal SOC
Latest Articles
- SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput
- New Number Formats for FFT IP Cores in Optical OFDM Transceivers
- Reducing Power Consumption of Embedded Dynamic Memories with ECCs
- NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference
- A 32-channel event-based bio-signal analog front-end with adaptive delta and pulse frequency encoding