Vendor: Synopsys, Inc. Category: Standard Cell Libraries

Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)

The Synopsys Duet Packages of Embedded Memories and Logic Libraries, part of Synopsys Foundation IP portfolio, offer an integrate…

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UMC 40nm ULP Available on request View all specifications

Overview

The Synopsys Duet Packages of Embedded Memories and Logic Libraries, part of Synopsys Foundation IP portfolio, offer an integrated portfolio of standard cell libraries, memory compilers and memory test and repair capability. The optimized combinations of high-performance and high-density SRAMs, register files, ROMs, standard cells, and Power Optimization Kits (POKs) provide all the elements needed to implement a complete system-on-chip (SoC). Options for overdrive/low voltage, process, voltage, temperature corners (PVTs), high-density SRAMs and multi-channel logic standard cells are also available, enabling designers to achieve the highest quality of results for their SoC in their specific application.

An additional High Performance Core (HPC) Design Kit provides a suite of high-speed and high-density memory instances and logic cells specifically designed to enable SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of the three.

Benefits

  • All the elements needed to implement a complete SoC, including high-performance and high-density SRAMs, register files, ROMs, standard cells, and Power Optimization Kits (POKs)
  • High-density embedded SRAMs optimized to generate the absolute minimum area and power enable designers to achieve aggressive area and power budgets
  • Multiple levels of memory power management features. Light Sleep, Deep Sleep and Shut Down modes enable array biasing with partial periphery shut down, full periphery shut down with data retention and a complete shut down without data retention
  • Yield-optimized standard cells with multiple threshold voltage and channel length variants

Silicon Options

Foundry Node Process Maturity
UMC 40nm ULP Available on request

Specifications

Identity

Part Number
dwc_duet_embedded memories_logic libraries_umc
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA
Contact Synopsys, Inc.

Learn more about Standard Cell Libraries IP core

Product How-to: Fully utilize TSMC’s 28HPC process

This article describes five areas where designers can take advantage of this new process with the latest logic library technology to optimize the performance, power and area of their system on chips (SoCs).

Using in-design physical verification to reduce tapeout schedules

Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and complexity of DRC rules is increasing and designs are getting bigger. The need for a better understanding of the manufacturing issues during the design phase raises concerns about how to best address these issues.

Methodology to lower supply voltage of standard cell libraries

Standard cells libraries are usually designed to operate at a specific value of supply voltage referred to as “nominal voltage”. This article details the performance trade-offs in terms of power consumption and speed when decreasing power supply voltage, as well as a methodology to determine the lowest value to use.

Why 28nm is the New Strategic Node?

If someone had predicted fifteen years ago that 28nm would still be the foundation for many new chip designs, the idea might have seemed unlikely. Process technology was advancing rapidly, and the industry’s attention was firmly fixed on shrinking geometries. Each new node promised more transistors, greater integration, and higher performance.

Frequently asked questions about standard cell libraries

What is Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)?

Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm) is a Standard Cell Libraries IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for umc Available on request.

How should engineers evaluate this Standard Cell Libraries?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Standard Cell Libraries IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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