Fault Tolerant Design of IGZO-based Binary Search ADCs
By Paula Carolina Lozano Duarte 1, Sule Ozev 2, Mehdi Tahoori 1
1 Karlsruhe Institute of Technology, Karlsruhe, Germany
2 Arizona State University Tempe, USA
Abstract
Thin-film technologies such as Indium Gallium Zinc Oxide (IGZO) enable Flexible Electronics (FE) for emerging applications in wearable sensing, personal health monitoring, and large-area systems. Analog-to-digital converters (ADCs) serve as critical sensor interfaces in these systems. Yet, their vulnerability to manufacturing defects remains poorly understood despite unipolar technologies' inherently high defect densities and process variations compared to mature CMOS technologies. We present a hierarchical fault injection framework to characterize defect sensitivity in Binary Search ADCs implemented in n-type only technologies. Our methodology combines transistor-level defect characterization with system-level fault propagation analysis, enabling efficient exploration of both single and multiple fault scenarios across the conversion hierarchy. The framework identifies critical fault-sensitive circuit components and enables selective redundancy strategies targeting only the most sensitive components. The resulting defect-tolerant designs improve fault coverage from 60% to 92% under single-fault injections and from 34% to 77.6% under multi-fault injection, while incurring only 4.2% area overhead and 6% power increase. While validated on IGZO-TFTs, the methodology applies to all emerging unipolar technologies.
Index Terms — Flexible Electronics, IGZO-TFT, Fault Injection, Binary Search ADC, Defect-Tolerant Design, Hierarchical Simulation.
To read the full article, click here
Related Semiconductor IP
- PVT sensor integrated SAR ADC in 12nm
- 12bit 500Msps High Speed General Purpose SAR ADC IP Core
- 12bit 4Gsps SAR General Purpose ADC IP Core
- 16bit 5Msps SAR General Purpose ADC IP Core
- 24-bit 320kHz Bandwidth ADC IP
Related Articles
- An Implementation Study on Fault Tolerant LEON-3 Processor System
- Why Hardware Root of Trust Needs Anti-Tampering Design
- An Outline of the Semiconductor Chip Design Flow
- Understanding the Importance of Prerequisites in the VLSI Physical Design Stage
Latest Articles
- Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
- Hardware-managed heterogeneous high-bandwidth memory and flash in LLM inference systems
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework