Extending Chip Lifetime with Safer Voltage Scaling
By Eyal Fayneh, proteanTecs
Reduce Infrastructure CAPEX While Boosting System Performance
What if your chips lived 20% longer without compromising performance, and even while reducing power consumption? How would it affect your product’s reliability and cost? What would be the effect on your profitability?
With the demand for longer-lasting chips growing across industries, designers and reliability engineers face increasing pressure to ensure their products perform correctly for the expected lifetime. Application stress is one of the key contributors to chip degradation over the years, as performance under demanding workloads leads to increased power consumption, higher temperatures, greater reliability risks, and eventually, reduced product lifespan.
This article explores an innovative approach to workload-aware and reliability-aware adaptive voltage scaling that is much safer than traditional methods. Therefore, it enables the use of fewer guard bands (i.e., reclaiming unutilized guard bands), significantly extending SoC lifetime.
Why Prolonging Chip Lifetime Matters
Datacenters, automotive systems, and consumer devices require installed chips to function reliably over extended periods. Hyperscale datacenters, for example, have publicly announced strategic business objectives that aim to reduce capital expenditure (CAPEX) and promote sustainability by stretching the useful life of servers. According to the table below1, this lifetime extension has increased Amazon’s quarterly net income by $0.9B. It has also increased the annual net income of Alphabet and Microsoft by $3B.
The table further shows that those giants performed a similar move to extend server lifetime a few years earlier, indicating a clear trend. Moreover, the impact on net income has increased from $2B-$2.7B in 2021 to $3B-$3.7B in 2023. This surge can be explained by the recent introduction of high-stress workloads, such as generative AI, which require much more computing resources. With the rising hardware expenses, it’s clear why hyperscalers strive to maximize chip lifetime more than ever.
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