Wafer Stacking Technology Promises Faster, Denser System-On-a-Chip (SOC)
Tachyon Semiconductor and Los Alamos National Laboratories Explore Applications
Naperville, IL - June 10, 2002 - A novel wafer-stacking process developed by Tachyon Semiconductor offers unprecedented speed and density advantages for multi-functional "System-On-a-Chip" (SOC) devices. These advantages have attracted the attention of Los Alamos National Laboratories, resulting in an agreement to explore and define the production of 3-D integrated devices.
At present, SOC devices are manufactured by building many different types of circuitry onto a single silicon wafer. Forcing disparate elements onto one wafer invariably leads to process compromises and prevents any meaningful optimization. Tachyon's wafer stacking process allows different circuitry elements to be built on several separate wafers, each wafer fully optimized for its specific components. The finished wafers are stacked, bonded, and interconnected with thousands of through-silicon "vias" to create a fully integrated device. This process was labeled as a "top new technology" in Electronic Design magazine's 2002 Top Ten Forecast.
Tachyon Semiconductor Corporation has been sub-contracted by the University of California and Timension Inc. (of Mountainview, CA) to adapt its technology for use in devices being developed by the US Department of Energy's Los Alamos National Laboratories (LANL). Under the agreement, Tachyon will produce a report detailing the production of an SOC device with separate layers for the microprocessor, flash memory, FPGA (programmable logic), and DRAM (mass memory).
Scott Johnston, Tachyon's Director of Engineering, states: "Our team is thrilled to be working with an organization like Los Alamos National Laboratories. Their reputation as one of the world's premier research and development labs makes it especially exciting for us to be helping them to apply our stacking technology."
Tachyon Semiconductor Corporation is a privately held fabless semiconductor and engineering design services company that has developed significant intellectual property concerning stacked memory and SOC integrated circuits. To find out more about Tachyon's technology, check out www.tachyonsemi.com on the World Wide Web.
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related News
- Tachyum Books Purchase Order to Build System with 25,000x ChatGPT4 Capacity and 25x Faster than Current Supercomputers
- QuickLogic Releases Aurora 2.6 with Expanded Operating System Support and Up to 15% Faster Performance
- proteanTecs Launches Solution for System Production Analytics Based on Chip Telemetry
- Andes and Arculus System Collaborate to Integrate iPROfiler™ into AndeSysC, Expanding Virtual Platform Support for RISC-V SoC Design
Latest News
- SEMIFIVE Accelerates Growth with 97% YoY Revenue Surge in H1 2026, Powered by ASIC Turnkey, Mass Production, and IP
- Andes Technology has shut down Condor Computing
- TIER IV joins JST’s Next-Generation Edge AI Semiconductor R&D Program to open-source AI chip designs for autonomous driving
- BrainChip Partners With Orama.AOI For AI-Fueled Defect Detection
- PUFsecurity, subsidiary of eMemory, Advances Hardware-anchored Trust for AI Infrastructure at OCP APAC 2026