TVS announces new CPU Verification tool development
February 23, 2015 -- TVS is pleased to announce the development of a new “Event Stream Generator”.
Processors (CPU, GPU, DSP, etc.) are becoming more complex and require more verification. The current best practise in processor verification is instruction stream generation.
The TVS instruction stream generator (asureISG) will have the following major features
- Offline generation: the instructions are generated in advance of simulation for quicker generation speeds.
- Sequence generation: sequences of instructions can push a design into the corners where the bugs lurk!
- Multicore support: asureISG can be programmed to generation instructions for multiple cores allowing it to generate sequences of instruction streams for multiple cores. Those sequences can interlaced with defined synchronisation points for multicore verification.
- Coverage support: coverage models can be built into the generation to help direct the generation.
asureISG is currently under development with TVS key clients but we are open to more early adopter partners who want to influence the development.
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related News
- Imperas and Metrics Collaborate to Jump Start RISC-V Core Design Verification Using Open Source Instruction Stream Generator
- eInfochips announces SPI4.2 and CCIR656 Stream Generator Design IP
- Mentor Catapult HLS Enables Stream TV's R&D Group SeeCubic to Develop Glasses-Free 3D Digital Display IP
- Siemens hardware-assisted verification validates Arm AGI CPU for scalable agentic AI
Latest News
- Arteris Deployed by Speedata for Data Center Compute
- Siemens to acquire Defacto Technologies to complement its EDA portfolio with automated SoC design creation
- Mach42 Completes £7M Funding Round, Led by IP Group With Investment From BGF and Foresight Group
- ELECTRA IC Unveils Comprehensive IP Core Suite for Next-Generation Post-Quantum Cryptography
- CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options