SystemC seen accelerating simulation
SystemC seen accelerating simulation
By Richard Goering, EE Times
February 26, 2003 (11:25 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030226S0013
SAN JOSE, Calif. SystemC is seeing increasing use as a way of accelerating simulation, according to speakers at the DVCon Design and Verification Conference. Meanwhile, speakers noted important milestones coming up in 2003 for the Open SystemC Initiative's (OSCI) standardization efforts.
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related News
- MachineWare announces new ARM processor simulation and SystemC profiling products, adds Windows support
- Net processors seen morphing into SoC
- Sun, ARM rewrite the rules for accelerating Java
- Synopsys and OCP-IP Members Jointly Develop SystemC Modeling Methodology for OCP-Based SoC Design
Latest News
- GF unveils roadmap to deliver the world’s most advanced FD-SOI platform for Physical AI
- GlobalFoundries marks Dresden expansion milestone, announces next-generation platform for Physical AI
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools