Optimization key to the future, says EDA pioneer
Dylan McGrath, EE Times
(09/18/2009 7:10 PM EDT)
SAN FRANCISCO—The greatest opportunity for EDA lies in providing optimization for system-on-chip designers as opposed to more functionality, according to a long-standing veteran of EDA.
"EDA as we know it today will be less feature introduction and more about optimization," said Jim Hogan, a 35-year veteran of EDA, IP and the broader semiconductor industry who is currently a managing partner at venture capital firm Vista Ventures LLC. Hogan goes way back in the EDA industry and was an influential executive at Cadence Design Systems Inc. for many years.
To read the full article, click here
Related Semiconductor IP
- AXI5 to/from AXI4 Bridge
- AXI5-Stream to/from AXI4-Stream Bridges
- APB5 to APB4 bridge
- UALink PHY + Controller
- General Purpose Low-Dropout (LDO) - TSMC
Related News
- ARM And Cadence Establish New Five-Year Agreement Targeting Design Chain Optimization
- CoWare Partners with PowerEscape for Power Optimization Software
- Legend Announces Software Tool for Semiconductor Process Optimization, Verification and Statistical Characterization
- iRoC Technologies Introduces SERPRO Services for Transistor-level Soft Error Rate Analysis and Optimization
Latest News
- SEALSQ and GlobalFoundries Partner to Accelerate Post-Quantum Cryptography and Quantum Computing Technologies
- Arteris Announces Collaboration with IC-Link by imec to Accelerate Next-Gen AI and HPC Silicon
- SambaNova Completes First Close of $1B Financing at $11B Valuation
- TAKUMI starts licensing new Warping IPs “TW270” and “TW290”
- Quintauris Announces Planned Leadership Transition