SynTest introduces DFT software that automatically stitches test-ready design blocks and cores together to improve the quality of IC and SoC designs

TurboDFT saves time, avoids errors Baltimore, Maryland, October 30, 2001 International Test Conference --SynTest Technologies, Inc. of Sunnyvale, California announced TurboDFTT, DFT software that integrates test-ready blocks and intellectual property cores for better SoC testability. TurboDFT works with any test-ready block or core and accepts RTL, gate-level and mixed-level design descriptions.

TurboDFT improves the quality of IC and SoC designs. With TurboDFT, test-ready design blocks or cores, such as scan cores; logic, memory or analog BIST cores; or boundary scan (JTAG) cores can be easily and automatically integrated (when compared to manual methods) and tested. TurboDFT accepts RTL, gate level and mixed-level design descriptions, and generates test benches for the blocks or cores.

According to Ravi Apte, Vice President of Marketing and Business Development at SynTest, "Our customers are increasingly doing more designs with test-ready blocks and cores. One of the most time-consuming processes is manually stitching together the intellectual property cores from different sources and in different forms, while maintaining the design's testability. TurboDFT makes this process easier by automatically integrating the cores and generating top-level test benches."

Apte added, "We believe TurboDFT can shave weeks from this otherwise tedious manual process, and this could be a 10 or 20% saving in time over the manual process for complex designs. Also, because TurboDFT's process is automatic, the number of errors is reduced when compared to a manual process."

TurboDFT works with any test-ready design block as well as design blocks produced using SynTest's scan, boundary scan and BIST tools to improve a SoC design's testability. It produces top-level test benches for hierarchical designs.

TurboDFT runs on Sun Solaris, HP-UX and Linux platforms. It supports Verilog and VHDL designs. It is available now. The US price is $50,000 (USD).

About SynTest
SynTest Technologies, Inc. develops and markets DFT and fault simulation software tools and offers consulting services throughout the world to semiconductor companies, ASIC designers and test groups. The Company's products improve an electronic design's testability and fault coverage and result in not only reduced defect levels and costly tester time, but also reduced slippage in time-to-market.

SynTest's DFT products include memory BIST for testing embedded memories, logic BIST for "at-speed" testing of logic blocks, a boundary-scan (JTAG) test suite, a DFT integration tool suite, DFT testability checkers for RTL and gate-level netlists, a partial-scan and full- scan synthesis and ATPG tool suite and a super-fast concurrent fault simulator. For more information, visit www.syntest.com.

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Acronyms and definitions:
ASIC: Application Specific Integrated Circuits
BIST: Built-in Self-test
DFT: Design-for-Test
IP: Intellectual Property
JTAG: Joint Test Action Group
SoC: System-on-Chip

TurboBIST-LOGIC, TurboBIST-Memory, and TurboScan are trademarks of SynTest Technologies, Inc. All other trademarks are the property of their respective owners.

SynTest introduces DFT software that automatically stitches test-ready design blocks and cores together to improve the quality of IC and SoC designs