Syntacore's SCR RISC-V IP Now Supports Zephyr 4.3
April 21, 2026 -- Syntacore, a RISC-V processor IP and software tools specialist, announces full support for Zephyr 4.3 Real-Time Operating System (RTOS) in its SCR RISC-V IP portfolio.
Major features:
Added support for CLIC, ACLINT, and AIA (ACLINT+IMSIC) interrupt controllers- Implemented PMA Checker support
- Enabled support for Syntacore generic cache L2 and L3
- Implemented Syntacore GCC and LLVM (clang) compiler support
- Incorporated new extensions: Bitmanip, Scalar Crypto, and zicbom
Zephyr OS is pre-configured and tested for SCR cores, allowing developers to easily deploy real-time embedded applications. The operating system is ready to use out-of-the-box, supports multi-core configurations, and is regularly updated with professional technical support available.
To get Zephyr 4.3, please contact our sales/FAE team.
Explore Syntacore IP:
- High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor
- High-performance microcontroller core with a 12-stage dual-issue out-of-order pipeline and a high performance FPU
- High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, and cache coherency
Related Semiconductor IP
- High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor
- High-performance microcontroller core with a 12-stage dual-issue out-of-order pipeline and a high performance FPU
- High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, and cache coherency
- Efficient Linux-capable application core with a 9-stage in-order pipeline, an MMU, L1 and L2 caches, and cache coherency
- Efficient microcontroller core with a 5-stage in-order pipeline, privilege modes, an FPU, an MPU, L1 and L2 caches
Related News
- Zephyr 4.0 Now Available for SCR RISC-V IP
- Syntacore upgrades its SCR RISC-V IP: Packed-SIMD, Zicond and Zimop Extensions
- SiFive Sets New Bar for High-Performance RISC-V with Third-Generation Performance P550 and P570 IP
- Andes Technology and Mirabilis Design Announce Collaboration on System-Level Models for Andes RISC-V Processor IP
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