STMicro face-recognition processor includes FPGA core

STMicro face-recognition processor includes FPGA core
By Anthony Cataldo, EE Times
May 3, 2002 (1:30 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020502S0038

SAN JOSE, Calif. — Looking to design a face-recognition processor that wouldn't get bogged down by heavy-duty algorithms, researchers at STMicroelectronics developed a unique chip architecture that combines a configurable processor from Tensilica Inc. and an embedded FPGA core.

The image processor uses Tensilica's Xtensa processor running at 200 MHz and special instructions to cut through the tougher face-recognition algorithms used to process 250-line images. Using C code extensions tailored for the Xtensa processor, the chip can execute four of these algorithms in 1.26 seconds, versus 10.7 seconds using only C code. Using a database of 20 faces, the face-recognition algorithm itself took 68 percent of the total processing time, STMicro said.

Linked to the Xtensa processor through a special bus is an FPGA block, which serves to generate the C code extensions. "In this way the FPGA acts as a [Tensilica instruction extension] conta iner but it's also used as a programmable master/slave and for general purpose I/O," said STMicro researcher Francesco Lertora.

Designed as a research vehicle, the 5.5 x 5.5-mm test chip was built using 0.18-micron design rules.

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