Synopsys Updates CXL IP Portfolio for AI-Era Infrastructure

By Gary Hilson, EE Times | August 20, 2026

Synopsys’s latest Compute Express Link (CXL) IP offerings target one of AI infrastructure’s most persistent constraints: Memory capacity and bandwidth are struggling to keep pace with increasingly demanding models.

The company’s recently announced CXL 4.0 IP portfolio integrates a controller, IDE security module, silicon-proven physical layer, and verification IP, with support spanning CXL 4.0 and earlier generations of the interconnect.

The AI boom, now entering its inference and agentic era, has intensified long-running pressure on memory. In a briefing with EE Times, Ron Loman, product marketing manager for PCIe and CXL IP at Synopsys, said the bottleneck can be traced back as far as 2012. “There’s never been enough cache on chip. There’s never been enough DRAM accessible.”

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