Sidense Exhibiting at Common Platform Technology Forum
March 7, 2012 -- Ottawa, Canada and Santa Clara, Calif.
What
Sidense exhibiting at the Common Platform Technology Forum and discussing its 1T-OTP non-volatile memory IP
Where
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, California 95054
Booth 302
When
Wednesday, March 14, 2012
11:30AM to 6:00PM
Who
Tom Schild, VP Worldwide Sales and Marketing
Jim Lipman, Marketing Director
For more information or to schedule a meeting with Sidense please contact:
Jim Lipman
Sidense
jim@sidense.com
925-606-1370
About Sidense
Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (LNVM) IP solution. With over 90 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense SiPROM, SLP and ULP memory products, embedded in 200-plus customer designs, are available from 180nm down to 28nm and are scalable to 20nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, please visit www.sidense.com.
About the Common Platform Technology Forum
Please join IBM, Samsung Electronics, Co., Ltd., and GLOBALFOUNDRIES at the 2012 Common Platform Technology Forum. The forum will showcase the alliance’s technological progress and how joint collaboration and innovation is setting the direction for industry-leading solutions to enable next-generation products.
Under this year’s theme, "A Decade of Invention…A World of Solutions," the forum will feature next-generation technologies and production-ready design and manufacturing solutions from the alliance and more than 20 of its ecosystem partners in our Partner Pavilion.
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related News
- Sidense Exhibiting at Common Platform Technology Forum
- Sidense Exhibiting at TSMC Open Innovation Platform (OIP) Ecosystem Forum
- Sidense Exhibiting its 1T-OTP Memory Solutions at TSMC Open Innovation Platform (OIP) Ecosystem Forum
- Sidense Exhibiting and Presenting a Paper at the TSMC Open Innovation Platform (OIP) Ecosystem Forum
Latest News
- JEDEC Advances DDR5 MRDIMM Ecosystem with New Memory Interface Logic and Expanded MRDIMM Roadmap
- Altera Brings Determinism to Physical AI Systems with Latest Release of FPGA AI Suite
- Mosaic SoC raises $3.8M to bring real-time spatial intelligence to every consumer device
- UMC Reports First Quarter 2026 Results
- Rambus Appoints Sumeet Gagneja as Chief Financial Officer