Sidense introduces 1T-Fuse(TM), an Embedded Non-Volatile Memory technology, in Logic CMOS process
Ottawa, Canada - November 21, 2005 - Sidense Corp., an Ottawa startup, announced today that it has developed an embedded non-volatile memory (NVM) intellectual property (IP) core, targeted to the most widely used standard logic digital CMOS process. The Sidense design is based on a patent pending technology, which does not require any additional masks or process steps, and utilizes only one transistor as a memory cell positioning it as a leader in area efficient NVM IP core solutions.
"Most of our competitors are either using larger structures which require change to the process, or use technologies that are not easily scalable to 90nm and below. We have designed one-time-programmable (OTP), non-volatile memory macros that are very small and faster then other solutions on the market. Our 1T-FuseTM memory is extremely secure and very difficult to reverse engineer, if not impossible. This makes it ideal for secure code storage applications such as encryption keys", stated Xerxes Wania, President and C.E.O. of Sidense.
Sidense offers their IP as a hard macro, targeted towards different foundries and configurations with supporting documentation, test benches and design files. Sidense 1T-FuseTM has been silicon proven in 130nm and can be portable to 90nm, 65nm and below.
About Sidense
Sidense Corp., founded in 2004 by memory and IP veterans, focuses on developing Non-Volatile Memory (NVM) intellectual property (IP) cores, to be embedded onto standard logic digital CMOS Application Specific Integrated Circuits (ASICs) and custom Integrated Circuits (ICs). Potential applications include fuse and FLASH replacement, code storage, RFID, Unique ID, encryption, key storage and is also used in Digital Rights Management (DRM). They currently have offices in Mississauga and Ottawa, Canada. www.sidense.com
Related Semiconductor IP
- Generative AI Edge Processor
- AXI NoC Non-Coherent Mesh
- CXS c/d/Lite Verification IP
- USB OTG 2.0 with xHCI Verification IP
- DDR5 RDIMM Verification IP
Related News
- Sidense Qualifies 1T-OTP Non-Volatile Memory for MagnaChip 180nm Mixed-Signal and HV CMOS Process
- Kilopass XPM Non Volatile Memory IP Qualified on TowerJazz 130nm CMOS
- Javelin Semiconductor chooses Kilopass Non Volatile Memory Intellectual Property Core for MIPI RFFE Digital Interface in Next-Generation CMOS Power Amplifiers
- Kilopass XPM IP Provides Non Volatile Memory in IBM 65nm LPE Process For Portable Devices That Demand Lower Leakage Than Bulk CMOS Provides
Latest News
- ChipAgents Collaborates With NVIDIA to Launch Build-A-Chip-Bench for Autonomous Chip Design and Implementation
- Quintauris and Microchip Technology join forces to grow RISC-V® adoption
- BrainChip Launches Sequora: Edge AI That Doesn’t Just Recognize — It Understands and Responds
- GlobalFoundries selected to operate two new semiconductor fabs in New York under landmark U.S.-Japan initiative
- Siemens’ Tessent ecosystem enables direct test pattern execution via PCIe and USB