TSMC's R&D chief sees 10 years of scaling
DylanMcGrath, EETimes
10/25/2011 2:45 PM EDT
SANTA CLARA, Calif.—The path is clear for continued semiconductor scaling using FinFETs for the next decade, down to the 7-nm node, according to Shang-Yi Chiang, senior vice president of R&D at foundry giant Taiwan Semiconductor Manufacturing Co.
Beyond 7-nm, the most pressing challenges to continued scaling will come from economics, not technology, Chiang said in a keynote address at the ARM TechCon event here Tuesday (Oct. 25).
To read the full article, click here
Related Semiconductor IP
- Camera Post-Processing IP
- DC-DC Split-Pi Boost-Buck Converter
- Deep learning accelerator
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
Related News
- Solutions to CMOS scaling limits are appearing, conference hears
- AVR32-based SoC Offers High Throughput Solution for Compute-intensive Embedded Control Applications; Combines Two Ethernet MACs, 480 Mbps USB with On-chip PHY, LCD Controller with High throughput CPU, Dynamic Frequency Scaling
- Intel's Bohr sees at least 10 more years of scaling
- EDA vendors cashing in on move to FinFETs
Latest News
- VeriSilicon Introduces CPP2000 Camera Post-Processing IP for Embodied Robotics and Mobile Vision Applications
- Infineon opens the world's largest fab for power semiconductors and analog/mixed-signal technologies in Dresden
- Tenstorrent Sets New Performance Records, Launches TT- Ascalon S, and Expands Across Japan
- Chips&Media Signs APV codec IP Licensing Deal with North American Big Tech, Establishing the ‘Second Front’ Against Apple’s ProRes
- Chipsolve Technologies Appoints Balaji Kanigicherla as Chairman of the Board