Elliptic Technologies Offers First Security Engine for Multi-Core System-On-Chip Designs

March 31, 2010 - - Ottawa, Canada -- Security IP provider Elliptic Technologies today announced that it has released the latest version of its CLP-600 Security Protocol Accelerator (SPAcc) which now includes the ability to support multiple processor cores from a single hardware security engine.

Elliptic has found that many of its customers are using multiple processors in their new SoC designs. Customers have asked Elliptic to create a single, powerful hardware security engine in these designs and share the engine among one or more processor cores. This virtualization capability is now available in the CLP-600 SPAcc.

The CLP-600 also offers support for traffic management to ensure that customers can achieve their latency goals for voice and video traffic. This capability is supported through partial packet processing combined with multiple command/status queues. Large packets can be broken into multiple sub-commands allowing smaller, latency sensitive packets to be interleaved with the large packets to prevent head of line blocking.

To meet the needs of multiple security applications such as IPsec, WiMAX, SRTP, MACsec and 3GPP/LTE, the CLP-600 is configured at build time to support the mix of cipher and message authentication algorithms required by customers. These options include multiple AES modes (CBC, CCM, XTS and GCM), DES/3DES, RC4, SNOW 3G as well as hashing algorithms such as HMAC/SHA-1/MD5, HMAC/SHA-256 and AES-XCBC.

“Multi-core processors such as the ARM Cortex™-A9 and MIPS32® 1004K™ have become increasingly popular for high-performance SoC applications.” said Richard White, President and CEO of Elliptic Technologies. “Our goal with the CLP-600 Security Protocol Accelerator is to offer customers the ability to virtualize their security engine and implement a single, high-performance, cost efficient, offload engine for these demanding applications.”