Samsung announces 90-nm process for system-on-chip designs

Samsung announces 90-nm process for system-on-chip designs
By Semiconductor Business News
May 29, 2002 (10:28 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020529S0013

SEOUL -- Samsung Electronics Co. Ltd. today announced a 90-nm (0.09-micron) logic process for system-on-chip (SoC) designs, featuring effective gate lengths of 70-nm and speed increases of 30% compared to company's current 130-nm (0.13-micron) technology.

The Korean chip maker said its 90-nm logic technology uses copper dual-damascene processes for interconnects and ultra-shallow junction technology as well as 1.6-nm thin-gate insulating film. The process shrinks die sizes by about 50% compared to the existing 0.13-micron technology generation, Samsung said.

With today's announcement, Samsung declared that it has jumped into the so-called "nano-technology" arena with other large integrated device manufacturers.

Samsung said its initial applications for the 90-nm SoC process technology will be in mobile phone central processing units, which has been identified as a core business for the company in the future. Samsung said it plans to est ablish a 90-nm process portfolio for high-speed circuits, low-voltage devices, embedded memory, and mixed-signal RF functions by 2003.

Mass production for the 90-nm process technology is slated for 2004, when other 0.09-micron ICs are expected to enter volume manufacturing based on the International Technology Roadmap of Semiconductor (ITRS), Samsung said.

Samsung said its memory density in 90-nm SoC products will be improved with an SRAM cell size of 1.25 micron². Other major chip makers are targeting six-transistor SRAM cell sizes below 1 micron² in the next-generation 90-nm process technology. For example, Texas Instruments Inc. this month disclosed plans to shrink its SRAM cells to a size of 0.97 micron² in the 90-nm process generation compared to 1.97 micron² in TI's 130-nm technology (see May 22 story).