Dolphin Integration announce the availability of new ROM TITAN and ultra low leakage standard cell library SESAME BIV at TSMC 55 nm LP eFlash
Grenoble, France – July 15, 2014 -- Dolphin Integration are proud to announce the availability of the new ROM TITAN and the ultra low leakage SESAME BIV at 55 nm LP eFlash.
These two new products come to enrich the large panoply of Dolphin Integration at 55 nm LP eFlash, which now count: RAM, DpRAM, ROM, foundry sponsored ultra-high-density standard cell library and ultra-low-leakage standard cell library.
The new architecture of ROM, named TITAN allows Dolphin Integration users to:
- reduce their die cost thanks to key patent for high density with a single metal programming layer, earning its qualifier of sROMet
- extend their battery life thanks to a minimal leakage in memory periphery
- facilitate integration with a large number of MUX options and high flexibility for address range
Tha ultra low leakage standard cell library allows for its part to:
- reduce drastically the leakage (1/700) compared to a traditional standard cell library
- power always-on logic power domains thanks to direct battery connection
- reduce the die cost thanks to the absence of regulators (low BoM)


For more information about the:
- sROMet TITAN TSMC 55 nm LP eF click here
- SESAME BIV TSMC 55 nm LP eF click here
Or contact Dolphin Integration Library Marketing Manager at libraries@dolphin-ip.com
About Dolphin Integration
Dolphin Integration contribute to "enabling mixed signal Systems-on-Chip". Their focus is to supply worldwide customers with fault-free, high-yield and reliable kits of CMOS Virtual Components of Silicon IP, based on innovative libraries of standard cells, flexible registers and low-power memories. They provide high-resolution converters for audio and measurement, regulators for efficient power supply networks, application optimized micro-controllers.
They put emphasis on resilience to noise and drastic reductions of power-consumption at system level, thanks to their own EDA solutions missing on the market for Application Hardware Modeling as well as early Power and Noise assessment In addition strong experiences in ASIC/SoC design and fabrication, plus privileged foundry portal even for small or medium volumes, makes them a genuine one-stop shop covering all customers’ needs for specific requests.
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related News
- Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm
- Dolphin Integration announce availability of their 6-Track Standard Cell Library SESAME HD for the 65 nm LP process
- NASA Selects Ridgetop Group to Develop an Innovative Modular SiGe 130 nm Cell Library
- Dolphin Integration announces a new generation of ultra-dense standard cell library for GSMC 0.18 mm uLL eFlash process
Latest News
- First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC
- MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- SEALSQ’s Subsidiary IC'Alps Advances QASIC Roadmap for Sovereign, Quantum-Resistant Application-Specific Integrated Circuits
- NVMe 2.4 Update Adds Post-Quantum Security, Power Controls
- Agentrys Raises $24.5 Million to Build Agentic Design Automation for Chipmakers