Rockwell seeks 50 percent design cycle reduction
Richard Goering, EE Times
(03/15/2007 12:10 AM EDT)
SAN JOSE, Calif. — Avionics electronics firm Rockwell Collins has initiated a five-year effort to cut its engineering cycle time by 50 percent, according to Linda Snow-Solum, senior director of enterprise infrastructure management at that company. In a presentation Wednesday (March 14), she outlined Rockwell's drive to integrate tools and processes at the enterprise level.
Snow-Solum was a speaker in the management track at the Mentor Graphics User-to-User conference. She discussed how Rockwell Collins is centralizing its tool selection and support, reducing engineering handoffs, cutting schematic development time, and using an internally developed "peer review" tool.
(03/15/2007 12:10 AM EDT)
SAN JOSE, Calif. — Avionics electronics firm Rockwell Collins has initiated a five-year effort to cut its engineering cycle time by 50 percent, according to Linda Snow-Solum, senior director of enterprise infrastructure management at that company. In a presentation Wednesday (March 14), she outlined Rockwell's drive to integrate tools and processes at the enterprise level.
Snow-Solum was a speaker in the management track at the Mentor Graphics User-to-User conference. She discussed how Rockwell Collins is centralizing its tool selection and support, reducing engineering handoffs, cutting schematic development time, and using an internally developed "peer review" tool.
To read the full article, click here
Related Semiconductor IP
- UALink 200G v1.0 Verification IP
- CCSDS SCCC Demapper and Turbo Decoder
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
Related News
- Synopsys Collaborates with GLOBALFOUNDRIES to Deliver Up to 50 Percent Power Reduction for Designs Using the 22FDX Platform
- Xilinx Planahead v2.2 Tool Delivers Up To 2X Performance Boost And 50% Design Cycle Reduction For Virtex-4 FPGAs
- Cadence Introduces Indago Debug Platform, Improving Debugging Productivity by up to 50 Percent
- Fuji Xerox Reduces Silicon Area by More than 50 Percent Using Synopsys ASIP Designer
Latest News
- Marvell, Microsoft and Oracle Establish OCP Working Group to Standardize Data Center Hardware Security
- At GAITA, PUFsecurity Shows How PUFrt and PUF-Based HSMs Give Agentic and Physical AI a Verifiable Root of Trust
- QuickLogic Secures Six-Figure eFPGA IP Contract for Automotive Industrial SoC
- Faraday Powers Intelligent Sensing with New 14nm MIPI C/D Combo PHY IP
- Cadence Wins Five 2026 TSMC OIP Partner of the Year Awards