RISC-V Foundation clarifies '100 errors' reports

April 27, 2017 // By Peter Clarke, eeNews Europe

The RISC-V Foundation has commented on reports that tests performed by researchers at Princeton University had found more than 100 errors resulting from the memory consistency model of high-performance implementations of the RISC-V processor instruction specification.

Krste Asanović, chairman of the RISC-V Foundation, has published an article at the Foundation's website pointing out that although a particular RISC-V design failed over 100 tests, with reference to the C11 high-level programming language, a single change to the RISC-V instruction set architecture (ISA) specification could eliminate all these failures

The article stresses that the unmodified Rocket core did not exhibit any illegal behavior because it does not reorder memory accesses aggressively. The problematic behavior occurs when additional re-ordering is done that would be legal under the current version of RISC-V. "It is important to note that a failed litmus test does not correspond one-to-one with errors in the MCM, as a single change in the MCM could remove all litmus test failures," Asanović said in his blog.

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