Princeton finds bugs in RISC-V architecture
April 19, 2017 // By Peter Clarke, EENews Europe
If uncorrected these errors could cause hard-to-debug errors, crashes and security vulnerabilities in software on RISC-V chips, the research team said, but added that changes are being made to the specification ahead of a "formal release" of the ISA later in 2017.
RISC-V is an open-source instruction set architecture originally developed for research and education but which is now becoming a standard open architecture for industry implementations with backing from numerous companies including AMD, Google, Hewlett Packard, Huawei, IBM, Micron, Microsemi, Microsoft, Nvidia, NXP, Rambus, Qualcomm, Samsung and Western Digital. The technology, if widely adopted, could be disruptive to the business models of established IP licensors such as ARM and Imagination.
To read the full article, click here
Related Semiconductor IP
- 64-Bit 8-stage superscalar RISC-V processor
- Multi-core capable RISC-V processor with vector extensions
- 32 Bit - Embedded RISC-V Processor Core
- ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
- ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
Related News
- Phison Selects Andes RISC-V Cores for its First aiDAPTIV+ AI Solution, Marking a Major Milestone in AI Architecture
- TransEDA tool aims to catch bugs earlier, improve design reuse
- 0-In Announces Breakthrough Deep Counterexample Technology to Find the Toughest RTL Bugs Before Silicon
- Netspeed Raises $10M in Series C Funding Led by Intel Capital to Bring Machine learning to SoC design and architecture
Latest News
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
- Vayavya Labs and Tenstorrent Partner to Accelerate RISC-V Hardware and Software Development Through Virtual Platform Modeling
- RaiderChip’s Edge NPU reaches more than 50 Generative AI Models with the addition of Qwen3.8-27B