Rambus Signs Memorandum of Understanding with Intel
Company to provide technology and design resources for evaluation effort of XDR™ memory architecture
Los Altos, California, United States -- Nov. 07, 2007 -- Rambus Inc., one of the world's premier technology licensing companies specializing in high-speed memory architectures, has signed a memorandum of understanding with Intel to explore possible uses for Rambus' family of XDR™ memory solutions.
Rambus plans to dedicate certain technology and design resources to the effort and the evaluation will be done on Intel’s silicon process technology. The Company stressed that Intel was only evaluating the technology for possible future uses and has no specific product plans for the XDR memory technology at this time.
The XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); FlexPhase™ circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for scalable point-to-point signaling on the data bus.
About Rambus Inc.
Rambus is one of the world's premier technology licensing companies specializing in the invention and design of high-speed memory architectures. Since its founding in 1990, the Company's patented innovations, breakthrough technologies and renowned integration expertise have helped industry-leading chip and system companies bring superior products to market. Rambus' technology and products solve customers' most complex chip and system-level interface challenges enabling unprecedented performance in computing, communications and consumer electronics applications. Rambus licenses both its world-class patent portfolio as well as its family of leadership and industry-standard interface products. Headquartered in Los Altos, California, Rambus has regional offices in North Carolina, India, Germany, Japan, Korea and Taiwan. Additional information is available at www.rambus.com.
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related News
- GigaDevice Announces a Patent Licensing Agreement with Rambus
- Rambus Delivers 112G XSR/USR PHY on TSMC 7nm Process for Chiplets and Co-Packaged Optics in Networking and Data Center
- Greg Lang Joins Rambus Board of Directors
- Rambus Reports Second Quarter 2020 Financial Results
Latest News
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’
- OpenAI and Broadcom unveil LLM-optimized inference chip
- RAAAM Selects Avnet ASIC as its VCA Partner for TSMC’s 2nm GCRAM Development and Qualification