R&D Crisis Ahead?
Ed Sperling, Semiconductor Engineering
June 26th, 2014
Too many choices and uncertainty turn ROI for new chip architectures into riskier gambles—and force a rethinking of what’s next.
Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and improved architectures?
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related News
- Advantest steps up SoC test development in new U.S. R&D center
- Taiwan targets IC design as next expansion phase, plans SoC R&D park
- MIPS to take $2 million charge for acquiring Lexra's R&D
- NeoMagic pushes ahead with new SoC strategy, posts $6.8 million loss
Latest News
- JEDEC Advances DDR5 MRDIMM Ecosystem with New Memory Interface Logic and Expanded MRDIMM Roadmap
- Altera Brings Determinism to Physical AI Systems with Latest Release of FPGA AI Suite
- Mosaic SoC raises $3.8M to bring real-time spatial intelligence to every consumer device
- UMC Reports First Quarter 2026 Results
- Rambus Appoints Sumeet Gagneja as Chief Financial Officer