Qualcomm defines format for 3-D chip stress
Rick Merritt, EETimes
9/22/2010 5:24 PM EDT
SAN JOSE, Calif. – Qualcomm has teamed up with Synopsys to define a new data exchange format it believes could be critical for supporting 3-D chip stacks that use through silicon vias. Qualcomm has already gotten support from at least one foundry and one chip assembler for the so-called Stress Exchange Format.
"We think industry needs to get together on this, everyone needs this enablement—we'll compete on other things," said Mark Nakamoto, a Qualcomm engineer.
To read the full article, click here
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related News
- Qualcomm and Himax Technologies Jointly Announce High Resolution 3D Depth Sensing Solution
- Foundry model under stress
- Chip execs see 20 nm variants, 3-D ICs ahead
- 3D Graphics on Xilinx ZC702 Board
Latest News
- UMC Reports First Quarter 2026 Results
- Rambus Appoints Sumeet Gagneja as Chief Financial Officer
- SEMI Reports Worldwide Silicon Wafer Shipments Increase 13% Year-on-Year in Q1 2026
- POLYN Technology Announces Tapeout of Automotive Chip
- QuickLogic Establishes New Banking Relationship and Secures $10 Million Revolving Credit Facility