Qualcomm defines format for 3-D chip stress
Rick Merritt, EETimes
9/22/2010 5:24 PM EDT
"We think industry needs to get together on this, everyone needs this enablement—we'll compete on other things," said Mark Nakamoto, a Qualcomm engineer.
To read the full article, click here
Related Semiconductor IP
- Dual Channel 8b D/A Converter - TSMC T40ULP
- Dual Channel 12b D/A Converter - TSMC T40ULP+ESF3
- 8bit D/A Converter - TSMC 22nm ULP
- 12bit 2MSps A/D Converter - TSMC T22ULP
- TSMC 2nm 1V2 GPIO
Related News
- Qualcomm and Himax Technologies Jointly Announce High Resolution 3D Depth Sensing Solution
- Foundry model under stress
- Xilinx Ships World's First Heterogeneous 3D FPGA
- SENSIO 3D Decoder integrated in Christie SKA-3D processor
Latest News
- Perceptia Releases Design Kit for pPLL03 on Samsung Foundry 14LPU Platform
- Brite Semiconductor Releases 28nm High-Performance SAR ADC IP, Driving Upgrades for High-Speed Signal Chain Applications
- Synopsys Updates CXL IP Portfolio for AI-Era Infrastructure
- BrainChip Launches Symphony Community Akida Bundle For IBM’s Workload Management Solution
- StarIC Appoints Dr. Masum Hossain as Chief Technology Officer