PMC-Sierra extends MIPS-based communications processors to 400 MHz

PMC-Sierra extends MIPS-based communications processors to 400 MHz
By Semiconductor Business News
April 5, 2001 (1:38 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010404S0056

BURNABY, British Columbia -- PMC-Sierra Inc. today (April 4) said it has redesigned its MIPS-based communications processors to deliver maximum performance and minimum power consumption in network infrastructure equipment.

The third-generation RM5231A and RM5261A microprocessors are pin-compatible upgrades of the company's RM5231 and RM5261 chips. The new designs deliver up to 400 MHz of processing performance, while consuming less than one watt of power, said PMC-Sierra. The previous designs operated at 250 MHz.

The RM5200A processors extend the superscalar architecture of the RM5200 family, enabling the simultaneous execution of one integer and one floating-point instruction in a single microprocessor clock cycle, said PMC-Sierra. Like their predecessors, the new processors are true 64-bit chips with 64-bit data paths, and 64-bit ALUs.

The RM5231A is the 32-bit memory and peripheral interface version of the family, while the RM5261A offers 64-bit external access.

The processors include independent 32-Kbyte instruction and 32-Kbyte data caches. They also provide external peripheral and memory access at bus speeds exceeding 100 MHz.

PMC-Sierra said its MPD unit (formerly QED) is the first MIPS processor licensee to move its microprocessor design into volume production at Taiwan Semiconductor Manufacturing Co., using an advance 0.18-micron process.

The 64-bit RM5261A is available in speeds up to 400 MHz and packaged in a 208-pin quad flat pack (QFP). Pricing for a 250-MHz version starts at $30. The RM5231A (with 32-bit peripheral interfaces) is available with speeds up to 350 MHz and housed in a 128-pin QFP package. In quantities of 10,000, the 250-MHz 5231A processor is priced at $20.