Open-Silicon To Present Technical Papers On SoC Architecture and Verification at IP-SOC 2013
MILPITAS, Calif. -- November 6th, 2013– Open-Silicon, Inc., a leading semiconductor design and manufacturing company, announced today that it would present two technical papers at IP-SOC 2013 in Grenoble, France.
Mrugesh Walimbe, MTS Function Manager, and Mahesh Penugonda, Senior Engineer VLSI for Open-Silicon, will present “Auto Clock Generation for an SoC”. This paper addresses the growing complexity of SoCs in terms of functionality and the challenges that SoC designers face with requirements to generate different clock frequencies and associated clock requirements. The paper details the novel idea of automatic clock generation and what it means for SoC design engineers.
Ganesh Venkatakrishnan, Lead Engineer for Open-Silicon, will present “Reusable Test-Case Methodology for SoC Verification”. This paper addresses a novel test-case methodology for SoC verification to achieve high levels of reusability. It details the challenges of a traditional SoC test-case methodology and proposes a solution. It also provides a sample implementation that can be modified or enhanced based on SoC needs.
What: Paper Presentation – “Auto Clock Generation for an SoC”
Who: Mrugesh Walimbe, MTS Function Manager, and Mahesh Penugonda, Senior Engineer VLSI, Open-Silicon
When: Session 5: From IP to System On Chip Architecture – Wednesday, Nov. 6, 4:45 – 6:00 p.m.
Where: Kilimandjaro Room
About Open-Silicon, Inc.
Open-Silicon, a leading supplier and developer of customer-specific products (CSPs), provides ASICs, platforms, concept-to-parts development, customized IP, low-effort derivative design, and state-of-the-art manufacturing solutions. With Open-Silicon, customer’s benefit from global engineering including an ARM® Technology Center of Excellence, advanced SerDes integration, 2.5D interposer-based package engineering, experienced architects, leading-edge physical design methodology, and embedded software development, all leveraging the industry’s best technology from both Open-Silicon and the open market. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related News
- Open-Silicon to Present on Design-Lite at IP-SOC Days Event in Santa Clara
- Inside Secure Embedded Security Expert to Speak at the IP-SOC 2013 Conference and Exhibition
- Cadence Unveils New Palladium Z2 Apps with Industry's First 4-State Emulation and Mixed-Signal Modeling to Accelerate SoC Verification
- Radiation-Tolerant PolarFire® SoC FPGAs Offer Low Power, Zero Configuration Upsets, RISC-V Architecture for Space Applications
Latest News
- Arteris Deployed by Speedata for Data Center Compute
- Siemens to acquire Defacto Technologies to complement its EDA portfolio with automated SoC design creation
- Mach42 Completes £7M Funding Round, Led by IP Group With Investment From BGF and Foresight Group
- ELECTRA IC Unveils Comprehensive IP Core Suite for Next-Generation Post-Quantum Cryptography
- CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options