On-chip nets look to rewire next-gen ICs

Richard Goering, EE Times
(12/26/2005 9:00 AM EST)

Santa Cruz, Calif. — Silistix Ltd. and STMicroelectronics have come up with very different approaches to a widespread problem: how to keep the fixed buses that link today's systems-on-chip from running out of steam.

Startup Silistix may have the most revolutionary plan. The company announced last week that it is developing electronic design automation and intellectual-property (IP) support for its Chain interconnect fabric. Chain is a self-timed, packet-based network built on extensive academic research in asynchronous logic, which supporters believe can solve a range of problems in ASIC and application-specific standard-product design.

STMicroelectronics, meanwhile, offered a December preview of its STNoC, a synchronous network-on-chip that comes with a new, ringlike "Spidergon" topology for connecting IP blocks. It offers a next-generation alternative to the current STBus, and will be available for both internal projects and external ASIC customers after test chips are run sometime next year.

Champions of the relatively new network-on-chip concept aim to replace fixed buses with a packet-based approach and a layered methodology. Advocates say it will provide much faster data transmission, more flexibility and easier IP reuse compared with conventional shared buses. But some research implementations have also resulted in area and power overhead, and a potential hit in latency.