MorethanIP releases a new version of its 10/100/1000 Ethernet MAC Core featuring a configurable 8/32-Bit Client interface
May 25, 2003 - MorethanIP releases Version 3.2 of its 10/100/1000 Ethernet MAC Core featuring a configurable 8/32-Bit Client interface for improved system level and embedded processor performance. With Version 3.2 the integration with standard interfaces like PCI, POS-PHY L3 or SPI 4.2 becomes simpler and seamless with an Altera Atlantic compatible FIFO client interface.
For applications that require the implementation of embedded processor (e.g. Routing, Switching, Firewall, Masquerade,...) the 10/100/1000 MAC core is also available with a direct 32-Bit Avalon Bus Interface that provides seamless connectivity to Altera Niostm embedded processor environments. An integration with ARM processor with 32-bit AHB bus is planned.
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related News
- CCIX Consortium Releases CCIX Base Specification Revision 1.1 Version 1.0 with Support for 32GT/s
- CAST Introduces MAC-SEC-MG IP Core for Secure 10G+ Ethernet SoC Designs
- MIPS Technologies and TSMC form strategic alliance to deliver "hard" versions of MIPS 32 and 64 Bit Processor Cores
- MorethanIP ships 2nd Generation 10GbE MAC Core
Latest News
- First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC
- MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- SEALSQ’s Subsidiary IC'Alps Advances QASIC Roadmap for Sovereign, Quantum-Resistant Application-Specific Integrated Circuits
- NVMe 2.4 Update Adds Post-Quantum Security, Power Controls
- Agentrys Raises $24.5 Million to Build Agentic Design Automation for Chipmakers