Mobiveil to Exhibit at DAC in Avery Design Systems' Booth, Showcasing Portfolio of IP, Platforms, Solutions for Storage, IoT, Networking, Enterprise Markets
Highlights Longstanding Avery/Mobiveil Partnership
MILPITAS, CALIF. –– June 14, 2017
WHO: Mobiveil, Inc., a fast growing supplier of silicon intellectual property (IP), platforms and IP-enabled design services
WHAT: Will showcase its portfolio of IP, platforms and solutions for the storage, IoT, networking and enterprise markets at the Design Automation Conference (DAC) in Avery Design Systems’ Booth #229. Mobiveil Chief Executive Officer Ravi Thummarukudy will be available to discuss its long-standing partnership with Avery that pairs Avery’s verification IP with Mobiveil’s PCI Express, NVM Express, DDR4/3 and LDPC IP.
WHEN: June 19-21 from10 a.m. until 6 p.m.
WHERE: Austin Convention Center in Austin, Texas
About Mobiveil
Mobiveil is a fast‐growing technology company that specializes in the development of Silicon Intellectual Property (SIP), platforms and solutions for the storage, IoT, networking and enterprise markets. It leverages decades of experience in delivering high‐quality, production‐proven, high-speed serial interconnect SIP cores, and custom and standard form factor hardware boards to leading semiconductor companies worldwide. For the PCI Express-based Flash Storage market, Mobiveil developed NVMStor™, a subsystem comprised of GPEX™, the PCI Express Controller, NVM Express Controller (UNEX™), Universal Memory Controller (UMMC™) and a Flash Memory Controller. Mobiveil is headquartered in Milpitas, Calif., with engineering development centers located in Chennai and Bangalore, India, and sales offices and representatives located in U.S., Europe, Israel, Japan, Taiwan and China.
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related News
- Mobiveil and Avery Design Systems Partner to Provide SoC Designers a Fully Verified and Compliant PCIe 5.0 IP Solution
- Mobiveil and Avery Design Systems Extend Partnership to Accelerate Design and Verification of NVMe 2.0-Enabled SSD Development
- Ausdia Solves Critical Design Flow Gap with OneSource Constraint Translation at DAC 2025
- DAC 2025: Towards Multi-Agent Systems In EDA
Latest News
- Arteris Deployed by Speedata for Data Center Compute
- Siemens to acquire Defacto Technologies to complement its EDA portfolio with automated SoC design creation
- Mach42 Completes £7M Funding Round, Led by IP Group With Investment From BGF and Foresight Group
- ELECTRA IC Unveils Comprehensive IP Core Suite for Next-Generation Post-Quantum Cryptography
- CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options